Circuit for connecting sequentially a plurality of devices to be tested

Abstract

A circuit for connecting sequentially a plurality of devices to be tested to a test apparatus. The circuit is of a structure which allows one device to be connected to the test apparatus at one time. The circuit includes a scanner for scanning the devices under test. The includes a shift register which performs shift operation in response to a scan command signal, AND circuits each having one input to which an output of the shift register is applied and the other input to which a signal indicating presence or absence of the associated device under test is applied, and a NOR circuit having inputs supplied with the outputs of the AND circuits, respectively. Further, the circuit includes NAND circuits each having one input to which the output of the corresponding one of the AND circuits is applied and the other input to which a pin card relay drive signal is applied. Still further, a binary coded decimal (BCD) conversion ROM is included to which the output of the NOR circuit is applied as an enable signal are provided. A relay incorporated in each of pin cards provided in association with the devices under test is driven by the output of the corresponding one of the NAND circuits to connect the corresponding device under test to a measuring apparatus. IC device test apparatus can be realized inexpensively with a simple structure.