Efficient high speed n-word comparator

Abstract

The efficient high-speed N word comparator receives a plurality of digital inputs which are simultaneously compared by conducting a digital to analog conversion on each input signal and comparing the analog signals in a plurality of weighted analog comparators. Each comparator conducts a balance between an associated input signal and the remaining input signals providing an output indication if the associated signal is an extremum value. The outputs of the comparators are then encoded to provide an address of the digital input of the extremum value and to select the input value through a multiplexer. The address and the value are then provided to subsequent circuitry for processing. Simultaneous comparison of all signals provides significantly reduced ripple delay while reducing the requirements for hardware allowing monolithic implementation for a larger plurality of inputs.