The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 1992
Filed:
Jun. 30, 1989
Gerald Corrigan, Chicago, IL (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A totally self-checking memory cell array apparatus (30) has an array (31) of memory cells (32) selectively addressed by row and column decoders (33, 35) which receive unidirectional error detecting code signals as address inputs (34, 36). Data, as a multiple bit data word (A, B, C.sub.1, C.sub.2), is stored in the array (31) in unidirectional error detecting code form. Cells in each row (1-8) of the array have two separate row select connection lines (45 and 45a) for coupling the cell to data and data complement (46, 46*) connections. Error detection circuits (44, 47) are provided which determine errors by comparing the data and data complement lines for each data bit read out of the array and for detecting when multiple bit data words read out of the array are not coded in a unidirectional error detecting code format. The above apparatus provides error indications in case of any unidirectional errors in the row or column input address signals or the row or column decoders, or any unidirectional error corruption of the data stored in the memory cell array. This is achieved without completely duplicating each memory cell in the array and all row and column decoder circuitry.