Adaptive lock time controller for a frequency synthesizer and method

Abstract

An adaptive lock time controller for a phase locked loop having dividers for generating first and second loop timing signals, a phase detector, a voltage controlled oscillator, and a charging circuit for generating at least a first control signal for converging the output frequency to one or more predetermined frequency channels and a second control signal for maintaining the output frequency substantially constant, comprises a synchronization generator, a phase lock detector, and a control signal selector. The synchronization generator is responsive to the phase detector for synchronizing the phase lock detector. The phase lock detector detects phase locked and unlocked conditions by generating a count representative of the phase difference between the first and second loop timing signals. When the count generated exceeds a predetermined count, a phase locked condition exists, otherwise the loop is unlocked. The control signal selector selects the first control signal during the predetermined time interval when the phase unlocked condition is detected, and the second control signal when the phase locked condition is detected.