The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 1992
Filed:
Dec. 03, 1991
Steven D Millman, Mesa, AZ (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A CMOS logic circuit uses a boost transistor responsive to a pulse signal to rapidly charge and/or discharge the output node during predetermined transitions of the input signal and provide a selectable slew rate for one edge of the output signal. A pulse generator circuit provides the pulse signal of predetermined width at a first transition of the input signal and disables the pulse signal and boost transistor before the following transition to avoid adversely effecting the opposite edge of the output signal. The width of the pulse signal and the size of the boost transistor determines the slew rate of the output signal for the edge under control. Many types of logic circuits such as inverters, NAND gates and NOR gates may utilize dual boost transistors and pulse generator circuits for separate control over both output edge rates without adversely affecting the opposite edge.