High performance bit-sliced multiplier circuit

Abstract

An apparatus for performing high performance multiplication in a computer central processor unit which implements a sliced design configuration. Each slice changes its 'personality' by virtue of receiving consecutive bits of the multiplicand. The receipt of consecutive bits by each slice eliminates the need for the interconnection of successive slices in separate chips. Thus, the apparatus allows the avoidance of significant timing delays, inherent in such interchip connections, which diminish computer system multiplication performance, and allows the multiply cycle time to be as fast as a latch-to-latch transfer across chips. Each slice may include a binary multiplier for forming a product of two numbers on an iterative basis, an accumulator connected to the multiplier for adding the products from the multiplier, and a carry-out register connected to the accumulator for storing carry-out data.