The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 1992

Filed:

Mar. 01, 1991
Applicant:
Inventor:

Sachiyuki Abe, Suwa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B / ; H03L / ; H03L / ;
U.S. Cl.
CPC ...
331 46 ; 331 49 ; 331 57 ; 331158 ; 331185 ; 331186 ;
Abstract

A semiconductor integrated circuit device comprises a first oscillator circuit driven by a first voltage for generating a first clock signal employed as the internal system clock signal for an internal circuit in the integrated circuit device and a second oscillator circuit driven by a second voltage lower than said first voltage for generating a second clock signal. A voltage boost circuit generates a stepped up voltage based on the second clock signal, which stepped up voltage is higher than the first voltage and is supplied to the first oscillator circuit and the internal circuit as their circuit source voltage. In another embodiment, an oscillation detecting circuit detects whether or not the first oscillator circuit is in an oscillating or non-oscillating state and, then, generates a clock selection control signal of a first type when the first oscillator circuit is in a non-oscillating state and generates a clock selection control signal of a second type when the first oscillator circuit is in an oscillating state. A clock signal selecting circuit is connected to receive either the first type or the second type clock selection control signal for respectively selecting either the second or the first clock signal for output. The oscillation detecting circuit is adapted to cease the oscillation of the second oscillator circuit when the first oscillator circuit is in its oscillating state.


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