The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 30, 1992
Filed:
Sep. 09, 1991
William H Gulliver, Gilbert, AZ (US);
Carl C Hanke, Mesa, AZ (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A phase lock loop (PLL) reduces output phase jitter by averaging an input clock signal and a delayed input clock signal. A control signal selects between the input clock signal and the delayed input clock signal for providing a reference clock signal for the phase lock loop. The output oscillator signal of the PLL is divided by a predetermined integer value for providing the control signal to select between the input clock signal and the delayed input clock signal. The PLL establishes phase lock to the input clock signal during a first state of the control signal. The PLL next establishes phase lock to the delayed input clock signal during a second state of the control signal such that the average value of the output clock signal of the PLL is substantially constant.