Method and circuitry for reducing output transients resulting from

Abstract

Circuitry for actively reducing the effects of ground voltage fluctuations in integrated circuits is described. An input buffer circuit including an output transistor 30 is provided along with a compensation circuit that is designed to reference the base of transistor 30 to an internal ground node of the integrated circuit. The compensation circuit includes a control diode 46, compensation transistors 42 and 43, bias resistors 40, 41 and 45 and diode chain 47, 48 and 49. In operation, the compensation circuit prevents the undesirable switching of output transistor 30 under low input voltage conditions by actively coupling the base of transistor 30 to internal ground through two conducting compensation transistors 43 and 42. Under these conditions, control diode 46 remains reverse biased allowing current flow through diode string 47, 48, and 49 which establish a threshold voltage to set the level at which compensation transistor 43 turns on. Once compensation transistor 43 turns on, a reference voltage is established on the base of transistor 30 which remains at a fixed level above internal ground as determined by the collector to emitter voltages of transistors 42 and 43 in the saturated state. Voltage transients that appear on the internal ground node and the emitter of transistor 30, are coupled to the base of transistor 30 and erroneous switching of this device is prevented. Under high input voltage conditions, diode 46 becomes forward biased and the threshold voltage is not overcome, thereby preventing the switching of transistor 43 and permitting the base of transistor 30 to remain at a high logic level.