The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 1992

Filed:

Mar. 01, 1991
Applicant:
Inventors:

Keiji Tanaka, Saitama, JP;

Kenji Nakazawa, Saitama, JP;

Shiro Suyama, Saitama, JP;

Kinya Kato, Saitama, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
357 2314 ; 357 237 ;
Abstract

The thin film transistor comprises source and drain regions, a channel forming region formed between the source and drain regions, a first (main) gate for turning on or off the transistor, and in particular at least one second (sub-) gate for reducing turn-off leakage current. When the n-channel transistor is turned off, for example, a negative voltage is applied to the main gate to form a p-channel layer in the channel forming region under the main gate and a positive voltage is applied to the subgate to form an n-channel layer in the channel forming region under the subgate, for instance, so that a pn junction can be formed between under the main gate and the subgate to reduce the turn-off leakage current. The above-mentioned disclosure can be clearly applied to p-channel transistors. Further, the above four-terminal transistor can be simply modified to a three-terminal transistor by connecting the main gate to the subgate via a diode or a capacitor or by directly connecting the drain region to the subgate. Further, the above three-terminal transistor can be manufactured in accordance with only the ordinary device manufacturing process.


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