Receiver designed with large output drive and having unique input

Abstract

A high voltage level input protection, high capacitance output IC clock receiver uses a ratioed CMOS buffer for the output drive and the receiver includes a low resistance input circuit having a pair of series connected large area input diodes physically located beneath the pad in an input network including a pair of gate controlled diodes in parallel therewith and a low value input resistor connected between the pad diodes and the gate controlled diodes. An N+ resistor receives the CMOS level output on a large metal bus from which metal interconnects fan-out to apply the clock signal to a plurality of loads in synchronism with diminished delay and increased reliability. Thus, reducing the resistance required in the input protection circuit improves the synchronism. Synchronism between the original clock signal input and the single diminished delay of the clock signal output from the CMOS buffer is maintained due to the 1 nanosecond clock input rise and fall time inherent in the subject clock receiver due to the low impedance (10 ohms) of the under the pad large diodes, the protection network input resistor of extremely low value (60 ohms) which accounts for the fast rise and fall time and permits the use of the large single delay buffer with fast rise and fall time.