Vlsi clocking system using both overlapping and non-overlapping clocks

Abstract

A clocking methodology for VLSI chips which uses global overlapping clocks plus locally or remotely generated non-overlapping clocks. Two overlapping clocks and two non-overlapping clocks are thus available in each block of a chip for use as timing edges. The global overlapping clocks are used where possible to provide timing advantages, while the non-overlapping clocks are used to eliminate race conditions as data propagates down a pipeline of transparent registers. Generally, one non-overlapping clock has an edge which must fall before a clock edge of the other non-overlapping clock rises and an edge which must rise after a clock edge of the other non-overlapping clock falls. These signals may be applied to adjacent stages to prevent race conditions; however, the 'dead' time between the falling of one clock edge and the rising of the other clock edge has performance costs. Overlapping clocks are used whenever such race conditions can be avoided, as at the ends of the register pipeline, with the resultant performance improvement. The non-overlapping clock signals are preferably derived from the overlapping clock signals inside each block rather than globally so that it is easier to control the skew between phases of the non-overlapping clock signals. Such use of local non-overlapping clock generators in each block also reduces the amount of capacitive loading on the global overlapping clock network, thereby allowing faster edges and smaller skews on the global overlapping clock which further improves the performance of critical timing paths which use the global overlapping clock.