The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 1992
Filed:
Aug. 08, 1990
Sakae Tanaka, Tokyo, JP;
Yoshiaki Watanabe, Tokyo, JP;
Katsuo Shirai, Tochigi, JP;
Yoshihisa Ogiwara, Tochigi, JP;
Seikosha Co., Ltd., Tokyo, JP;
Nippon Precision Circuits Ltd., Tokyo, JP;
Abstract
A silicon thin film transistor array includes a plurality of silicon thin film transistors in an array-like form, each silicon thin film transistor including an insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating layer formed on the insulating substrate containing the gate electrode, a pair of first impurity contained silicon layers formed on the gate insulating layer in such a manner as to transversely cross a terminal part of the gate electrode, an intrinsic silicon layer formed on the pair of first impurity contained silicon layers and on the gate insulating layer between the pair of first impurity contained silicon layers in such a manner as to connect the pair of first impurity contained silicon layers, a protective insulation layer formed on the intrinsic silicon layer, and a source electrode and a drain electrode formed at contact parts of the pair of first impurity contained silicon layers; gate wiring for connecting the gate electrodes of the silicon thin film transistors to each other; and source wiring for connecting the source electrodes of the silicon thin film transistors to each other.