The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 1992
Filed:
Jan. 28, 1991
Takeshi Sugoh, Yokosuka, JP;
Yasuhiro Sugimoto, Yokohama, JP;
Kabushiki Kaisha Toshiba, Kanagawa, JP;
Abstract
An ECL circuit is designed such that at the beginning of the falling of the output level, the current flowing to an output terminal is rapidly led in the direction where it will be reduced, the potential of the output terminal at this time is directly detected, and a pull down transistor is controlled through a feedback loop, thus assuring high-speed operation and low power consumption. A control circuit is provided to regulate the collector current of the pull down transistor, which is used to drop the level of the potential at the output terminal. This control circuit is so designed that the base current of the pull down transistor is controlled by the operation of another, single transistor, and no capacitor which will obstruct the circuit integration is employed to drive the pull down transistor. The structure of this circuit is therefore advantageous in realizing higher integration.