Static random access split-emitter memory cell selection arrangement

Abstract

This invention relates generally to the static, random access, semiconductor memory arrays which incorporate split-emitter memory cells. The latter are accessed during a read cycle of a selected memory cell by precharging all the bit lines of unselected memory cells associated with the word line of the selected cell. This is accomplished by switchably connecting a voltage source to all the unselected bit lines which charges their bit line capacitances. Then, when read current sources are switchably connected to both the selected and unselected memory cells and the associated word line is switched to a WORD SELECT source, the read current associated with the unselected bit lines flows via charging switches to the precharge voltage sources and the read current associated with the selected bit lines along with dynamic current from uncharged selected bit line capacitances flows into the selected cell. This approach prevents large, dynamic bit line currents from discharging the bit line capacitances of the unselected cells into those cells along with read currents.