Ferroelectric capacitor memory circuit mos setting and transmission

Abstract

A memory circuit including a plurality of ferroelectric capacitors arranged in a matrix, setting MOS field effect transistors for setting both electrodes of each of the ferroelectric capacitor at the same electric potential, and transmission MOS field effect transistors for transmitting information to the ferroelectric capacitors, and having a construction in which two word lines are provided corresponding to each line of the ferroelectric capacitors, one bit line is provided corresponding to each row of the ferroelectric capacitors, each of the transmission MOS field effect transistors is connected to one of the word lines and the bit line, and each of the setting MOS field effect transistors is connected to the other word line. Also disclosed is a memory circuit including memory cells each composed of ferroelectric capacitors arranged in a matrix and transmission MOS field effect transistors provided corresponding to the ferroelectric capacitors for transmitting information to the ferroelectric capacitors, line address decoders each provided corresponding to each group of the memory cells in each line for controlling the input and output of information to the ferroelectric capacitors, word lines provided corresponding to each group of memory cells in each the line for selecting line, and drive lines for commonly controlling the ferroelectric capacitors in the group of memory cells, and having a construction in which the word lines and the drive lines are connected to the line address decoders, and bit lines are provided corresponding to each row of the memory cells.