The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 09, 1992
Filed:
May. 31, 1991
Fujitsu Limited, Kawasaki, JP;
Fujitsu VLSI Limited, Kasugai, JP;
Abstract
An output circuit comprises first and second transistors connected in series between a first voltage source and an second voltage source such that the first and second transistors are turned on and turned off respectively in response to an input logic signal and a logic inversion thereof, third and fourth transistors connected in series between a third voltage source and fourth voltage source such that the third and fourth transistors are turned on and turned off respectively in response to the logic inversion of the input logic signal and the input logic signal, first and second power transistors connected in series between a fifth voltage source and a sixth voltage source such that the first power transistor is turned on in response to the turning-on of the first transistor and turned off in response to the turning-on of the second transistor, the second power transistor is turned on in response to the turning-on of the third transistor and turned off in response to the turning-on of the fourth transistor, wherein there are provided a first drive control circuit for detecting the turning-on of the second power transistor and disabling the turning-on of the first transistor with a delay such that the turning-on of the first transistor is prohibited for a predetermined interval even after the second power transistor is turned on following a turned off state and a second drive control circuit for detecting the turning-on of the first power transistor and disabling the turning-on of the third transistor with a delay such that the turning-on of the third transistor is prohibited for a predetermined time interval even after the first power transistor is turned on following a turned off state.