The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 09, 1992
Filed:
Oct. 10, 1990
Applicant:
Inventor:
Ted E Williams, Santa Clara County, CA (US);
Assignee:
HaL Computer Systems, Inc., Campbell, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
307452 ; 307443 ; 3072722 ; 307279 ; 365203 ; 36518904 ; 365222 ;
Abstract
CMOS domino logic is normally used only in two phases: precharge and logic evaluation. The invention uses a third phase to store data, which allows domino logic gates to be cascaded and pipelined without intervening latches. The inputs to this system must have strictly monotonic transitions during the logic evaluation phase and the precharge signal must be active during only the precharge phase. Furthermore, the pipelined system can feed its output back to the input to form an iterative structure. Such a feedback pipeline is viewed as a 'loop' or 'ring' of logic which circulates data until the entire computation is complete.