The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 1992

Filed:

Feb. 08, 1991
Applicant:
Inventors:

John F Schreck, Houston, TX (US);

Dennis R Robinson, Houston, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
307443 ; 307451 ;
Abstract

Resistors are used as controlling devices to control the rate at which output buffer transistors are turned OFF and ON to control transient noise. In one form the output buffer circuit comprises a NOR circuit having a first input coupled to a data input and a second input to an enable input, a NAND circuit having a first input coupled to the data input and a second input coupled to an enable input, a first inverter transistor pair having gates coupled to the output of the NOR circuit and having source-drain paths in series coupled to a reference, a second inverter transistor pair having gates coupled to the output of the NAND circuit and having source-drain paths coupled in series to a supply, a resistor coupled between in series between the source-drain paths of the first transistor pair and the supply, a resistor coupled in series between the second transistor pair and the reference, and a third inverter transistor pair with each gate of the third transistor pair coupled to one of the outputs of the first and second inverter transistor pairs and with the output of the third transistor pair coupled to the output of the buffer circuit.


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