Cmos output driver with transition time control circuit

Abstract

A single resistance permits a CMOS driver to have output devices that controllably transition 'fast off-slow on' and which are not simultaneously on while the driver switches states. The driver's output and supply currents contain reduced harmonics. The resistance is coupled to the gates of the output stage PMOS-NMOS devices, and forms an RC circuit with the intrinsic capacitance at the gates, extending the turn-on transition of the gate drive voltages. Each output device then turns on relatively slowly, but turns off normally. The output current transition times are essentially determined by the resistance and intrinsic capacitances. The resistance is implemented using polysilicon or diffusion, and preferably has a magnitude ten times the on-channel resistance of the input PMOS and NMOS devices driving the output stage. Because the resistance and intrinsic capacitances are essentially temperature and power supply voltage independent, and but slightly process dependent, the current output transition times can be controlled despite CMOS parameter variations. A 3-state embodiment of the CMOS buffer uses parallel coupled PMOS-NMOS devices to switchably couple in the resistance between both output gates when the enable signal is high. Second input PMOS and NMOS devices, connected in parallel across the first input PMOS and NMOS devices, turn on across the first input devices when the enable signal is low. A high enable signal enables the driver circuit, while a low enable signal uncouples the resistance and turns off both output PMOS and NMOS devices, putting the circuit's output in a high impedance state.