Apparatus for generating multiple phase clock signals and phase detector

Abstract

A phase detector circuit is provided for correction of operation of a synchronous delay line clock generator. The phase detector includes multiple edge detectors. The multiple edge detectors provide an override of any corrective action by the rest of the phase detector to the synchronous delay line output, notwithstanding presence or absence of any phase error of less than 360.degree., if the phase position of the delay line output signal is off by an integral multiple of 360.degree.. Multiple taps from daisy-chained or series-connected delay line elements are provided to the multiple edge detectors. The multiple edge detectors compare the edge produced by each such tap against (in the first instance) one division of divided clock signal or (for each subsequent tap) the result of the previous such comparison. In each such case, the comparison is accomplished by a not R, not S flip-flop receiving the signals to be compared. Although only two delay line elements need to be so tapped, tapping three or more such delay line elements ensures greater accuracy over a higher odd integral multiple of the clock signal. Also, even (as opposed to odd) integral multiples of the period of the clock signal are addressed by the part of the phase detector not including the edge detectors, since the phase detector receives only one of the divided clock signals. Faster correction of phase and frequency errors can be accomplished with an additional such phase detector that would be connected to the other division of the divided clock signal. This additional such phase detector would also include multiple edge detectors together receiving multiple taps from the delay line.