Dma controller having programmable logic array for outputting control

Abstract

A direct memory access controller coupled to a system bus for controlling a data transfer by a direct memory access comprises an internal bus, a data handler coupled to the system data bus and the internal bus for controlling an exchange of data between the system bus and the internal bus, a microsequencer which controls by microprograms parts of the direct memory access controller in units of one system clock cycle during one present transfer cycle, and a programmable logic array part supplied with a transfer request, a transfer mode information and at least portions of a transfer address and a byte count. The programmable logic array part is coupled to the internal bus and outputs control information required during a next transfer cycle during one transfer cycle which corresponds to a predetermined number of system clock cycles. Each data transfer between the input/output device and the memory device is controlled by the microprograms of the microsequencer in cooperation with the programmable logic array part.