The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 1992

Filed:

Apr. 16, 1990
Applicant:
Inventors:

Mitsuru Shimizu, Sakura, JP;

Syuso Fujii, Kawasaki, JP;

Shozo Saito, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365201 ; 36518909 ; 371 214 ;
Abstract

A semiconductor memory device such as dynamic random access memories comprises a work line drive circuit provided with two MOS transistors and a word line to which a word line drive signal is supplied, a substrate bias generation circuit for applying a bias voltage to a semiconductor substrate for MOS transistors, a burn-in mode detection circuit for detecting a burn-in test mode signal, and a substrate bias control circuit for controlling the substrate bias generation circuit. When the semiconductor memory device is subjected to a burn-in test, the power supply level Vcc is increased to raise the voltage of the word line drive signal as compared to that at a normal operation. Accordingly, a high level word line drive signal will be applied to cell transistors, thereby performing correct screening thereof.


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