The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 1992
Filed:
Aug. 22, 1990
Toshiaki Sakai, Kawasaki, JP;
Taichi Saitoh, Yokohama, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
An improved emitter coupled logic circuit suitable for high speed logic operation independent of capacitive load. With previous circuits as the load to be driven become heavier, the capacitive load required a longer time for discharge and the output signal was dulled, resulting in adverse effect on the logic operation when the output changed to a low level from a high level. A pulse has also been previously applied to a pull-down transistor connected between the output and a power source through a capacitor from an inverted phase output to actively discharge the capacitive load. However, when the capacitor is connected to the output it hinders the switching speed of a current switch. In the present invention, a transistor is provided an input circuit and a pulse is applied to a pull-down transistor from the transistor. As a result, an extra capacitive element is not connected to the output end, but a pulse is applied to the pull-down transistor. Accordingly, even if the capacitive load becomes heavier, the speed of the circuit is not harmed.