The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 1992

Filed:

May. 28, 1991
Applicant:
Inventors:

Nalin Kumar, Austin, TX (US);

Charles W Lin, San Antonio, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B44C / ; C23F / ; B29C / ;
U.S. Cl.
CPC ...
156644 ; 156645 ; 156652 ; 156655 ; 156656 ; 1566591 ; 156668 ; 156902 ;
Abstract

Method for making a multilayer electrical interconnect with stacked pillars between layers using a minimal number of conventional process steps. The method includes sputtering a chromium/copper/titanium trilayer on a dielectric base, depositing a patterned mask on the trilayer, etching the exposed trilayer, removing the mask, depositing a layer of polyimide over the unetched copper, forming a via in the polyimide above the copper, electrolessly plating nickel into the via, and polishing the interconnect to form a planar top surface.


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Kumar, Nalin. (1992). Multilayer electrical interconnect fabrication with few process steps (U.S. Patent No. 5118385). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5118385

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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