Pipelined register cache

Abstract

A pipelined register cache for increasing a computer processor's execution speed by reducing the time required to access register data. A register cache is implemented to keep often-used registers in high-speed storage immediately available to the processor's arithmetic and logic unit (ALU). The register cache is constructed using a number of individual register stages which are connected in series such that the register information contained in each register stage is passed from one register stage to the next in a First-In, First-Out (FIFO) queue arrangement. Each register stage stores a register address tag for identifying the particular primary register being represented in that register stage, and a data value representing the actual register contents. When a register that is not represented in the cache is needed for a calculation, the register information is first loaded from the primary register storage into the first register stage of the register cache. Once the register is represented in register cache, it can be accessed quickly by the arithmetic and logic unit for computations. As new register information is loaded into the register cache, the older register information in each register stage is passed from one register stage to the next. When register information overflows from the last register stage it is then placed back into the primary register storage.