Eprom memory array with crosspoint configuration

Abstract

In order to obtain an EPROM memory array with high compactness and the possibility of asymmetrically doping the channel, an array is proposed which comprises a substrate having a first conductivity type, first and second bit lines having the opposite conductivity type and extending parallel and mutually alternated in the substrate, a plurality of thick insulating material regions extending at least partially in the substrate above and parallel to the first bit lines, a plurality of floating gate regions extending above the substrate perpendicular to and between adjacent pairs of bit lines, a plurality of word lines extending perpendicular to the bit lines and above, but electrically insulated from, the floating gate regions, wherein the second bit lines extend up to the surface of the substrate and define unburied bit lines to the side whereof it is possible to provide enriched channel regions. The unburied bit lines can furthermore be subjected to a siliciding process to reduce series resistance.