The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 1992

Filed:

Jun. 01, 1990
Applicant:
Inventor:

Masakazu Shoji, Warren, NJ (US);

Assignee:

AT&T Bell Laboratories, Murray Hill, NJ (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; H03K / ; H03K / ;
U.S. Cl.
CPC ...
307443 ; 307448 ; 307451 ; 307452 ; 307491 ;
Abstract

Apparatus for compensating for the effect of a local condition on an active element in a portion of an integrated circuit. The apparatus includes a detecting element in the portion of the integrated circuit which is subject to the local condition and produces a response to the local condition which is proportional to the local condition's effect on the active element and a compensation element which is coupled to the detecting element and to the portion for reacting to the response of the detecting element tot he local condition by providing a compensating input to the portion which is proportional to the response and which compensates for the local condition's effect on the active element. An embodiment of the apparatus which compensates for leakage currents in FETs in a dynamic CMOS integrated circuit employs one or more FETs which are interspersed among active FETs as the detecting element and a current mirror as the compensating element. The current mirror responds to the leakage current in the detecting element FETs by producing a compensating current to compensate for the leakage current in the active FETs. The embodiment is employed in a dynamic NOR gate and a dynamic PLA.


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