The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 26, 1992
Filed:
Oct. 16, 1990
Applicant:
Inventors:
Joseph A Hoffman, Mannassas, VA (US);
Derwin L Jallice, Reston, VA (US);
Yogishwar K Puri, Vienna, VA (US);
Randall G Richards, Centreville, VA (US);
Assignee:
International Business Machines Corporation, Armonk, NY (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
307443 ; 307451 ; 307473 ; 3072962 ; 3072965 ; 307270 ; 307584 ;
Abstract
A full swing CMOS logic circuit provides fault tolerant, cold sparing of VLSI logic devices attached to a high speed bus. P-channel FET transistors are formed in an N-well which has a biasing transistor which effectively decouples the circuit when the circuit is not powered. The input/output interface of the cold spares have a high impedance and do not corrupt an interconnected electronic bus. The final drive transistors are reverse biased or clamped to zero to prevent any leakage paths.