The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 1992

Filed:

Sep. 28, 1990
Applicant:
Inventors:

Jose M Gobbi, Paris, FR;

Louis Le Berre, Les Ults, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307443 ; 307448 ; 3072991 ;
Abstract

Disclosed is a logic integrated circuit for which the time of switching over between two logic states, 0 and 1, is adjustable. In a logic operator such as an inverter, the switch-over time, at the output, is a function of the current put through by the load transistor or by the signal transistor. This time is adjustable, either as rising time or as fall time, by the replacement of at least one single-drain transistor by a multiple-drain transistor, the throughput rate of which is fixed by the number of connected drains. The disclosed device can be applied to pre-diffused (Si) circuits or pre-implanted (GaAs) circuits.


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