The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 1992
Filed:
Dec. 05, 1990
Jin Murayama, Kanagawa, JP;
Jun Fukazawa, Kanagawa, JP;
Fuji Photo Film Co., Ltd., Kanagawa, JP;
Abstract
A solid-state imaging device constructed according to the TSL system having a plurality of photodiodes arrayed in matrix form so as to serve as a group of pixels, a vertical selection gate line extending from a vertical scanning circuit, a horizontal selection gate line extending from a horizontal scanning circuit, and a signal read line. A projection made of an impurity layer identical to that of the photodiodes is formed at an end of each of the photodiodes. A first switching transistor is formed by interconnecting the vertical selection gate line made of a polysilicon layer so as to cross over an upper surface of each of the projections. A second switching transistor is formed by laminating a gate portion made of a polysilicon layer on the other upper surface of each of the projections. Horizontal selection gate lines are formed by connecting between the vertically arrayed gate portions and an interconnection made of a conductor layer such as an aluminum layer insulatively laminated above the polysilicon layer. Signal read lines are formed by a conductive layer fabricated by a process identical to that of the conductive layer, and each signal read line is interconnected so that the upper surface of the projection and the upper surfaces of the first and second switching transistors are shielded thereby, and that the signal read line does not come in contact with the conductive layer forming the horizontal selection gate line.