Method for manufacturing a stacked capacitor dram cell

Abstract

The method comprises the steps of: forming the transistor on a substrate and then depositing an interlayer insulating layer, and forming a design pattern of a first conductive layer by vertically etching it using a mask; horizontally overetching the pattern by using the etching process used for forming the pattern; depositing a first insulating film and then depositing the second conductive layer to the thickness needed to protect the first insulating film; vertically etching the second conductive layer, first insulating film and interlayer insulating layer by applying the mask used in vertically etching the first conductive layer; additionally depositing the second conductive layer; forming a design pattern of the second conductive layer by vertically etching it using a mask; horizontally overetching the pattern of the second conductive layer; depositing the second insulating film and then depositing a third conductive layer to have the thickness to protect the second insulating film; vertically etching the third conductive layer and second insulating film by applying the etching mask of the second conductive layer; additionally depositing the third conductive layer. The method attains larger effective capacitance in which a plate electrode layer surrounds even the lower surface of a storage electrode layer of the stack capacitor without using any extra mask.