The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 1992
Filed:
Feb. 20, 1990
David H Albonesi, Hudson, MA (US);
Brian K Langendorf, Shrewsbury, MA (US);
John Chang, Morton Grove, IL (US);
John G Faase, Palo Alto, CA (US);
Michael J Homberg, Grafton, MA (US);
Prime Computer, Inc., Framingham, MA (US);
Abstract
The invention comprises a system bus apparatus and method for a multi-arm, multiprocessor computer system having a main memory and localized buffer cache memories at each processor. Each block of data in a cache includes tag bits which identifies the condition of the data block in relation to the corresponding data in main memory and other caches. The system bus (SYSBUS) comprises three subparts; 1) a MESSAGE/DATA bus, 2) a REQUEST/GRANT bus and 3) a BCU bus. The MESSAGE/DATA bus is coupled to every device on the system and is used for transferring messages, data and addresses. The REQUEST/GRANT bus couples between every device on an arm of the system and that arm's bus control unit (BCU). The BCU bus couples between the various BCUs. Both the MESSAGE/DATA bus and the BCU bus include ACK/NACK/HIT bits which are used when responding to messages received over the SYSBUS to inform the message-issuing device if the devices received the message and, if so, the condition of the data in relation to other caches and main memory. The protocol allows inconsistent copies of data to exist and prevents stale data from being used erroneously by monitoring the tag bits and the ACK/NACK/HIT bits. Further, under the appropriate conditions, a copy of the most recent data block may be transferred from one cache to another (with appropriate updating of tags) without updating the main memory. When a memory operation will bring about a situation where cache coherence can no longer be maintained, main memory is updated with the most recent copy of the data and the other caches are either updated or tagged as invalid.