The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 1992

Filed:

Feb. 27, 1991
Applicant:
Inventors:

Karl-Heniz Ideler, Spardorf, DE;

Stefan Nowak, Kalchreuth, DE;

Gunter Petzold, Nuremberg, DE;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03F / ;
U.S. Cl.
CPC ...
330251 ; 330 66 ; 330289 ; 3302 / ; 363132 ; 363 98 ;
Abstract

Switched transistors (T1 . . . through T4 . . .) are arranged in a bridge circuit such that a plurality of transistors (T1 . . . through T4 . . .) are connected in parallel in every bridge branch. These transistors are secured on a thermally and electrically conductive ring (R, R'), are symmetrically distributed over this ring (R1, R1'), and have a respective terminal electrically connected thereto. The connection to further terminals of the transistors (T1 . . . through T4 . . .) occurs essentially in rotationally-symmetrical fashion via large-area printed circuit boards (LE1 through LE6). Short connecting paths with low values of inductance are achieved with this arrangement. Furthermore, the waste heat from all transistors (T1 . . . through T4 . . .) is uniformly carried off via the rings (R1, R1'), so that all transistors (T1 . . . through T4 . . .) work at the same temperature. A uniform current division onto all transistors (T1 . . . through T4 . . .) connected in parallel is assured with this arrangement, even in a dynamic case.


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