The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 1992
Filed:
Mar. 25, 1991
Karl J Huehne, Austin, TX (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A logic circuit for receiving both CMOS- and CML-level input voltages in one embodiment performs a logical OR function. A reference bipolar transistor is coupled to a first power supply voltage terminal through a first resistor. A second bipolar transistor for receiving a CML-level input signal is coupled to the first power supply voltage terminal through a second resistor. Emitters of the bipolar transistors are connected together. A MOS transistor for receiving a CMOS-level input signal has a drain connected to a collector of the second bipolar transistor, and a voltage dropping portion seperate the source of the MOS transistor from the emitters of the reference transistor and the bipolar transistor. The input voltages control a constant current conducted from a current source connected to the source of the MOS transistor. The logic circuit base-to-emitter reverse bias caused by CMOS logic levels.