Method of forming stacked tungsten gate pfet devices and structures

Abstract

A manufacturing method is provided for producing a stacked semiconductor structure including: depositing a first thick passivating layer onto the base structure; forming first stud openings in the first thick passivating layer exposing at least one active region and/or one of the polysilicon lines; depositing a first layer of a conductive material to fill the first stud openings and define first contact studs, the upper part of some of the first contact studs comprising the gate electrodes of PFET devices; planarizing the structure to make the top surface of the first contact studs coplanar with the surface of the first thick passivating layer; depositing a thick insulating layer to form the gate dielectric of PFET devices and patterning it to define contact openings to expose selected first contact studs at desired locations; depositing a layer of polysilicon; patterning the polysilicon layer to define polysilicon lands containing the first contact studs at the desired locations; selectively implanting to define the source and drain regions of the PFET devices and interconnection conductors; depositing a cap layer; depositing a second thick passivating layer forming second stud openings in the second thick passivating layer to expose desired portions of the polysilicon lands and/or portions of the first contact studs; depositing a second layer of conductive material to define second contact studs; and planarizing the structure to make the top surface of the second contact studs coplanar with the surface of the second thick passivating layer.