Digital phase locked loop system

Abstract

A digital phase locked loop system uses a clock signal from an oscillator which is frequency-divided by a frequency divider, thereby causing a phase locked loop clock signal locked to the input signal being produced. At this time, the phase difference between the input signal and the phase locked loop clock signal is computed by a counter. Then, by setting a frequency dividing ratio on the basis of the computed figure, the phase locked loop clock signal from the frequency divider is locked to the input signal. Furthermore, to correspond to fluctuation when the input signal is digitally pulse-width modulated, the pulse width of the input signal is computed by counter on the basis of the clock pulse. The computed figures are converted to the values which match the minimum repeatable frequency of the input signal. After the frequency dividing ration correspolnding to the phase difference is set for the frequency divider, such a frequency dividing ratio can coincide the phase of the input signal and the phase of the phase locked loop clock signal in accordance with the converted figures corresponding to the frequency of the input signal. Namely, such a digital phase locked loop system as described above can be of a simplified construction and can produce the phase locked loop clock signal locked to the input signal with good characteristics, even with a wide range of fluctuations in the input signal.