The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 1992
Filed:
Sep. 09, 1991
Hiroshi Miyamoto, Hyogo, JP;
Kazutoshi Hirayama, Hyogo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
An address buffer circuit comprises a flip-flop circuit having first and second input nodes and connected between a power-supply potential and a ground potential. In addition, first, second and third transistors are connected in series in that order from the side of the ground between the first input node and the ground potential, to constitute a first input circuit, and fourth, fifth and sixth transistors are connected in series in that order from the side of the ground between the second input node and the ground potential, to constitute a second input circuit. An external address signal is applied to a control terminal of the first transistor, and a reference potential is applied to a control terminal of the fourth transistor. At the time of operating the address buffer circuit, the second and fifth transistors are first turned on, to bring the first and second input circuits into the operating state and then, to bring the flip-flop circuit into the operating state. Thereafter, the third and sixth transistors are turned off, to bring the first and second input circuits into the non-operating state.