The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 28, 1992
Filed:
May. 18, 1990
Applicant:
Inventors:
Norio Nakagawa, Kodaira, JP;
Katsuaki Takagi, Higashimurayama, JP;
Assignee:
Hitachi, Ltd., Tokyo, JP;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395325 ; 3642426 ; 36424292 ; 3642423 ;
Abstract
A memory management device which is connected in a virtual address space or a physical address space together with another device capable of becoming a bus master, is endowed with the function of detecting the bus request signal of the other device, interrupting an address translation process under execution and causing a processor to release a bus. Thus, the other device can be made the bus master without being kept waiting for a long time, and a system bug can be prevented which is attributed to such a fact that a wait time exceeds the data hold time of an input/output device connected to, for example, a direct memory access controller.