All digital phase locked loop

Abstract

An all-digital phase-locked loop (PLL) for synchronizing an output clock signal with a reference clock signal. The PLL has a multiple-tap, digital delay chain in its forward path for delaying the output clock signal, which delay chain is controlled by a digital number stored by a counter in its feedback path. A phase detector in the feedback path provides LEAD and LAG signals, the status of which indicates whether the output clock signal leads or lags the reference signal. In response to the LEAD and LAG signals, a digital sequencer in the feedback path generates the digital number and stores it in the counter. The digital sequencer changes the digital number until the state of the LEAD and LAG signals reverses, and then returns the counter back to its state prior to LEAD and LAG reversal, for synchronism. The digital sequencer also causes a phase reversal of the output signal where the number of delay taps needed for synchronism is large. As a result of the all-digital circuitry, use of unstable prior art voltage-controlled oscillators is obviated.