Asynchronous time division switch with increased traffic handling

Abstract

An asynchronous time division (ATD) switch for carrying out packet switching. In one embodiment a switch has 256 ports running at 155 M bits and is capable of switching incoming data cells at each of the input ports to any one of 256 output ports. At each input port a switch sequentially distributes the received data cells over 16 outputs each of which is connected to a different DMR circuit. There are 256 DMR circuits each having 16 inputs and 16 outputs. A DMR circuit is a fixed space switching device which has N inputs, N time intervals and N outputs and operates cyclically so that each input goes to each output for 1/Nth of the time. The inner stage of the ATD switch comprises 256 central switches each having 16 inputs and 16 outputs. Each central stage switch has its 16 inputs connected to 16 different DMR circuits. The fourth stage of the switch consists of another array of 256 output DMR circuits with each central switch being connected to 16 different output DMR circuits. Each input DMR has its outputs connected to 16 different output ports. The internal circuitry of the ATD switch runs on 20 M bits. When a data cell is received at an input port its destination is derived from a header attached to the cell. Control circuitry enables the receiving port to request three addresses to query three possible routes through the switch. The ability to provide this series of questions is given by staggering the windows through which an output port can communicate with the central switches. Although data streams are received asynchronously the operation of the ATD switch is synchronous.