Nrz to cmi (ii) encoding circuit

Abstract

A NRZ/CMI (II) code converter comprising a D-type flip-flop for retiming a series of NRZ data bits received thereto with a clock synchronized therewith, an OR-gate connected to said one output of the D-type flip-flop to compose space bits of a series of said received NRZ data bits and a transmitted clock, and a delay element connected to the output of said OR-gate. The converter also comprises another OR gate connected to a negative output of said D-type flip-flop and another D-type flip-flop having a clock input connected to the output of said OR-gate. These elements function to compose mark bits of a series of the NRZ data bits with clock pulses and to generate two-divided alternative mark bits. An exclusive OR-gate is connected to the output of said another OR-gate and the output of said another D-type flip-flop. In the exclusive OR-gate, mark bits are alternatively generated at the mark bit portions of a series of the NRZ data bits, and clock pulses are composed with a series of the NRZ data bits at the space bit portions of a series of the NRZ data bits. In addition, mark bits and space bits of a series of the NRZ data bits can be independently processed for the same time, in order to generate the CMI (II) code.