The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 1992
Filed:
Nov. 01, 1990
Applicant:
Inventors:
Akitoshi Osaki, Itami, JP;
Akira Yamada, Itami, JP;
Assignee:
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
307601 ; 307603 ; 307606 ; 328 55 ;
Abstract
A delay circuit composed of a plurality of series circuits connected to each other in parallel, wherein each of series circuits is composed of a switching element made of FET like N-channel transistor and a capacitor. And a semiconductor system which allows proper connection of other semiconductor systems containing different AC charcteristics by delaying internal clock, input pulse signal or output pulse signal by applying the delay circuit embodied by the invention.
Osaki, Akitoshi. (1992). Delay circuit and latch circuit for controlling setup time and hold time (U.S. Patent No. 5107153). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5107153
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile