Cmos type input buffer circuit for semiconductor device and

Abstract

A CMOS type input buffer circuit includes a CMOS inverter comprising a p-channel and n-channel transistors connected in series between a backup or main power source and ground. The input buffer circuit includes a first switching element connected between said CMOS inverter and ground. The input buffer circuit can include a second switching element connected in parallel with said p-channel transistor. A back-up mode signal is applied to both switching elements to turn ON the first switching element and to turn OFF the second switching element during a normal mode and to reverse both switching elements during a backup mode, in which the input buffer circuit is disabled. The input buffer circuit can be connected between a first and second circuit. The first circuit is powered from a backup or main power source. The second circuit is powered from the main power source. A backup detection circuit, connected to the main power source, provides the backup mode signal for the input buffer circuit. In a normal mode first and second circuits are active and a signal is passed through the input buffer circuit. In a backup mode only the first circuit is active and the input buffer circuit is disabled from passing a signal.