The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 31, 1992
Filed:
Aug. 30, 1990
Toshiyuki Kumagai, Tokyo, JP;
Hiroyuki Suzuki, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
A synchronization compensating circuit for use in a scanning type display circuit, comprises a first multistage delay circuit receiving a basic clock for generating K delayed clocks, a second multistage delay circuit receiving an output of the first multistage delay circuit for generating L delayed clocks, and a timing signal generating circuit receiving a horizontal synchronization signal for generating a latch signal. A first selection signal generation circuit latches a first phase of the basic clock and the K delayed clocks in response to the latch signal, and a second selection signal generation circuit latches a second phase of the basic clock and the K delayed clocks in response to the latch signal. A third selection signal generation circuit latches the L delayed clocks in response to the latch signal. Each of the first to third selection signal generation circuit generates a selection signal corresponding to a received clock fulfilling a predetermined condition. A selection circuit receives the basic clock and the K and L delayed clocks for outputting a delayed clock corresponding to the selection signal outputted from the first signal generation circuit in preference to the selection signal from the second and third selection signal generation circuits, and a delayed clock corresponding to the selection signal outputted from the second selection signal generation circuit in preference to the selection signal from the third selection signal generation circuit when the selection signal is not outputted from the first selection signal generation circuit.