Variable length pipe operations sequencing

Abstract

A sequence of instructions made up of stages is executed sequentially by the processor in a first mode (stack mode) such that, the Nth stage of the Ith instruction is processed simultaneously with the N+1 stage of the I-1 instruction. Similarly the N+1 stage of the I-1 instruction is processed at the sasme time as the N+2 stage of the I-2 instruction and so on. The processing unit maintains the execution of instructions in the same sequence as they were received by the processing unit by executing all sections of an instruction. Even though a stage may not be required for execution of a particular instruction, the processor must wait (i.e., execute a null instruction) for a time equivalent to a stage before processisng the next stage. The invention provides a second mode (non-stack mode) of execution such that unneeded or null instruction stages are bypassed without the processing order of the execution sequence being disturbed. Sequence logic determines the conditions necessary for a sequence of instructions to be executed in one or the other modes of execution. The processor switches back and forth between stack mode and non-stack mode of processing in order to keep the instructions executing in the same order as they are received by the processor. The non-stack mode of execution allows the processor to utilize wasted time and improve the performance of the processor while the stack mode avoids the need for complex and expensive logic to keep track of out of order instruction processing.