The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 24, 1992
Filed:
Aug. 13, 1990
Matthew K Adams, Dallas, TX (US);
Dallas Semiconductor Corporation, Dallas, TX (US);
Abstract
A clock monitor circuit which is frequency-independent. The crystal terminals on a circuit being monitored for activity may be considered as an inverter combined with a phase delay. The innovative circuit has clock-output and clock-input terminals which are connected to the clock terminals on the circuit being monitored. When a rising edge appears on the clock-output terminal, the clock-input line is sampled: if the circuit being monitored is properly active, the level on the clock-input line will be high. Similarly, when a falling edge appears on the clock-output terminal, the clock-input line is sampled: if the circuit being monitored is properly active, the level on the clock-input line will be low. Whenever a low level is detected on a rising edge, or a high level on a falling edge, a counter chain will start counting down. The counter chain will be reset only when a high level is detected on a rising edge AND a low level is detected on the next falling edge. Thus, when the circuit being monitored becomes inactive, the counter chain will start to count down, and will eventually reach zero and generate a watchdog interrupt or reset.