The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 1992
Filed:
Jun. 18, 1991
Martin J Schwartz, Worcester, MA (US);
Robert D Becker, Shirley, MA (US);
Wang Laboratories, Inc., Lowell, MA (US);
Abstract
A system having a CPU, a main memory and a bus. A cache memory couples the CPU to the bus and is provided with circuitry to indicate the status of a data unit stored within the cache memory. One status indication indicates whether the contents of a storage position have been modified (dirty) since those contents were received from main memory. Another status indication indicates whether the contents of the storage position exist within another cache memory (shared). Each cache includes a bus monitor that monitors bus transactions. When data is read from system memory by a first cache a second cache determines if the data is shared. If yes, the second cache asserts a bus hold line and determines if the shared data is dirty. If yes, the second cache drives the corresponding data to the bus for storage within the first cache. For a system memory write, the second cache latches the data and determines if the data is shared. If yes, the second cache replaces its copy of the data with that latched from the bus. As such, no cache 'valid' status bits are required in that each cache is assured of having the most current version of data.