Signal processor including programmable logic unit formed of

Abstract

A programmable logic unit performs only monadic, dyadic logic bit level, rather than arithmetic, operations in order to achieve high speed. The unit is formed of section for each output bit position. Each section includes a general function block which simultaneously performs as desired, one or more of the operations cntl1.A.B, cntl2.A.B, cntl3.A.B and cntl4.A.B, wherein A, A, B, B and cntl1 to cntl4 are logic signals and control signals respectively. The inputs of the general function block are connected to a data distribution bus via a multiplex circuit. This connection between the multiplex inputs and the distribution bus can be selected as desired (once), so that the number of different logic operations that can be selected is very large.