Frequency counter and method of counting frequency of a signal to

Abstract

A dual-edge frequency counter and method for minimizing the effects of duty cycle modulation. In its simplest form, a dual-edge counter (50) includes a first counter (52) that accumulates reference clock pulses between successive rising edges of an input signal. An input signal is also applied to an inverter (54), which inverts the square wave signal prior to applying it to a second counter (56) that also accumulates reference clock cycles between successive rising edges of the inverted sensor signal. A summation junction (60) totals the accumulated counts from the first and second counters so that they can be averaged by a divider (62), which divides the total count by two. The technique is also employed in connection with a frequency counter that includes an integer counter (72) for totaling the number of cycles of the sensor signal occurring during a sample time defined by successive gate signals. The integer count, N, is then corrected for the compensated average of partial periods of the signal occurring at the beginning and the end of the sample time. The compensated average partial period corrects for variations in the sensor signal duty cycle caused either by noise superimposed on a sinusoidal signal produced by a quartz crystal (12) or as a result of variations in power supply level for the crystal oscillator.